This invention relates generally to insulated gate field-effect transistors (IGFETS), and more particularly the invention relates to reducing gate to drain capacitance in IGFETS including lateral and vertical MOSFETS.
Reduction of gate to drain feedback capacitance (C.sub.gd or C.sub.rss) in MOSFET devices is desired in order to maximize RF gain and minimize signal distortion. C.sub.gd is critical since it is effectively multiplied by the voltage gain of the device or C.sub.effective =C.sub.rss (1+gmR.sub.1) where gm is the transconductance and R.sub.1 is the load impedance.
Adler et al., U.S. Pat. No. 5,252,848 discloses an FET structure which includes a performance enhancing conductor shield covering the gate electrode and a portion of the drain region of the FET. A description of such a device operating as a 2 GHz RF transistor is in Technical Digest IEDM Conference, 1996, pages 87-90. While the external shield reportedly reduces C.sub.gd, the dominant component of C.sub.gd (gate over drain next to channel) is not shielded. Further, while the external shield is applicable to lateral MOS transistors (LDMOS), the external shield cannot be used with vertical transistors. Additionally, process costs in fabricating such devices can be high.
The present invention is directed to a MOSFET structure having more effective reduction of gate to drain parasitic capacitance.